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Fix some verilog issues

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This commit is contained in:
Koray Yanik
2023-10-03 22:30:36 +01:00
parent 06746f71fb
commit 9cc63a248e
8 changed files with 25 additions and 18 deletions
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4
rtl/cpu/alu.sv
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@@ -83,8 +83,8 @@ logic [ 7:0] xor_f;
logic [ 7:0] cp_a;
logic [ 7:0] cp_f;
assign alu_a = ({8{alu_ctrl_i.alu_op == ALU_OP_ADD}} & add_a) |
({8{alu_ctrl_i.alu_op == ALU_OP_SUB}} & sub_a) |
assign alu_a = ({8{alu_ctrl_i.alu_op == ALU_OP_ADD}} & add_a[7:0]) |
({8{alu_ctrl_i.alu_op == ALU_OP_SUB}} & sub_a[7:0]) |
({8{alu_ctrl_i.alu_op == ALU_OP_XOR}} & xor_a) |
({8{alu_ctrl_i.alu_op == ALU_OP_CP }} & cp_a);
assign alu_f = ({8{alu_ctrl_i.alu_op == ALU_OP_ADD}} & add_f) |

8
rtl/cpu/cpu.sv
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@@ -98,15 +98,15 @@ assign pc_bus[ 7:0] = ({8{bus_x_ctrl.dst == BUS_DST_PC_L}} & bus_x) |
always_ff @(posedge clk or negedge nreset) begin
if (!nreset)
sp_r[15:0] <= '0;
sp_r[15:8] <= '0;
else if (sp_we[1])
sp_r[15:0] <= sp_next;
sp_r[15:8] <= sp_next[15:8];
end
always_ff @(posedge clk or negedge nreset) begin
if (!nreset)
sp_r[ 7:0] <= '0;
else if (sp_we[0])
sp_r[ 7:0] <= sp_next;
sp_r[ 7:0] <= sp_next[7:0];
end
assign sp_we[1] = instr_valid & (
@@ -279,4 +279,4 @@ assign wdata_o = ({8{bus_x_ctrl.dst == BUS_DST_MEM}} & bus_x) |
`undef INST_BUS16
endmodule : cpu
endmodule : cpu

5
rtl/cpu/cpu_pkg.svh
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@@ -1,3 +1,6 @@
`ifndef CPU_PKG_SVH
`define CPU_PKG_SVH
package cpu_pkg;
typedef enum logic [2:0] {
@@ -142,3 +145,5 @@ typedef enum {
} pc_src_t;
endpackage : cpu_pkg
`endif /*CPU_PKG_SVH */

4
rtl/cpu/idec.sv
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@@ -102,7 +102,7 @@ assign is_ldh_n_a = instr_i[0] == 8'hE0;
assign is_ldh_a_n = instr_i[0] == 8'hF0;
assign is_ld_pnnnn_a = instr_i[0] == 8'hEA;
assign is_jr_cc_nn = (dec_x == 2'h0) & (dec_z == 2'h0) & dec_y[2];
assign is_jr_cc_nn = (dec_x == 2'h0) & (dec_z == 3'h0) & dec_y[2];
assign is_ld_rr_nnnn = (dec_x == 2'h0) & (dec_z == 3'h1) & ~dec_q & (dec_p != 2'h3);
assign is_ld_sp_nnnn = (dec_x == 2'h0) & (dec_z == 3'h1) & ~dec_q & (dec_p == 2'h3);
assign is_ldi_hl_a = (dec_x == 2'h0) & (dec_z == 3'h2) & ~dec_q & (dec_p == 2'h2);
@@ -117,7 +117,7 @@ assign is_inc_r = (dec_x == 2'h0) & (dec_z == 3'h4);
assign is_dec_r = (dec_x == 2'h0) & (dec_z == 3'h5);
assign is_ld_r_n = (dec_x == 2'h0) & (dec_z == 3'h6);
assign is_ld_rr_a = '0;
assign is_rla = (dec_x == 3'h0) & (dec_z == 3'h7) & (dec_y == 3'h2);
assign is_rla = (dec_x == 2'h0) & (dec_z == 3'h7) & (dec_y == 3'h2);
assign is_ld_r_r = (dec_x == 2'h1) & ((dec_z != 3'h6) | (dec_y != 3'h6));

6
rtl/cpu/regbank.sv
View File

@@ -17,9 +17,7 @@ module regbank (
input reg8_t reg8_rselect_i,
input reg16_t reg16_rselect_i,
output logic [ 7:0] reg8_rdata_o,
output logic [15:0] reg16_rdata_o,
output logic [15:0] hl_o
output logic [15:0] reg16_rdata_o
);
logic [15:0] reg_r [0:2];
@@ -55,8 +53,6 @@ module regbank (
reg_r[reg8_rselect_i[2:1]][15:8];
assign reg16_rdata_o = reg_r[reg16_rselect_i];
assign hl_o = reg_r[REG16_HL];
`include "sva_common.svh"
`SVA_DEF_CLK(clk)
`SVA_DEF_NRESET(nreset)