Fix some verilog issues

rtl/cpu/alu.sv

@@ -83,8 +83,8 @@ logic [ 7:0] xor_f;
 logic [ 7:0] cp_a;
 logic [ 7:0] cp_f;
 
-assign alu_a = ({8{alu_ctrl_i.alu_op == ALU_OP_ADD}} & add_a) |
+assign alu_a = ({8{alu_ctrl_i.alu_op == ALU_OP_ADD}} & add_a[7:0]) |
-               ({8{alu_ctrl_i.alu_op == ALU_OP_SUB}} & sub_a) |
+               ({8{alu_ctrl_i.alu_op == ALU_OP_SUB}} & sub_a[7:0]) |
                ({8{alu_ctrl_i.alu_op == ALU_OP_XOR}} & xor_a) |
                ({8{alu_ctrl_i.alu_op == ALU_OP_CP }} & cp_a);
 assign alu_f = ({8{alu_ctrl_i.alu_op == ALU_OP_ADD}} & add_f) |

rtl/cpu/cpu.sv

@@ -98,15 +98,15 @@ assign pc_bus[ 7:0] = ({8{bus_x_ctrl.dst == BUS_DST_PC_L}} & bus_x) |
 
 always_ff @(posedge clk or negedge nreset) begin
   if (!nreset)
-    sp_r[15:0] <= '0;
+    sp_r[15:8] <= '0;
   else if (sp_we[1])
-    sp_r[15:0] <= sp_next;
+    sp_r[15:8] <= sp_next[15:8];
 end
 always_ff @(posedge clk or negedge nreset) begin
   if (!nreset)
     sp_r[ 7:0] <= '0;
   else if (sp_we[0])
-    sp_r[ 7:0] <= sp_next;
+    sp_r[ 7:0] <= sp_next[7:0];
 end
 
 assign sp_we[1] = instr_valid & (

rtl/cpu/cpu_pkg.svh

@@ -1,3 +1,6 @@
+`ifndef CPU_PKG_SVH
+`define CPU_PKG_SVH
+
 package cpu_pkg;
 
 typedef enum logic [2:0] {
@@ -142,3 +145,5 @@ typedef enum {
 } pc_src_t;
 
 endpackage : cpu_pkg
+
+`endif /*CPU_PKG_SVH */

rtl/cpu/idec.sv

@@ -102,7 +102,7 @@ assign is_ldh_n_a    = instr_i[0] == 8'hE0;
 assign is_ldh_a_n    = instr_i[0] == 8'hF0;
 assign is_ld_pnnnn_a = instr_i[0] == 8'hEA;
 
-assign is_jr_cc_nn   = (dec_x == 2'h0) & (dec_z == 2'h0) & dec_y[2];
+assign is_jr_cc_nn   = (dec_x == 2'h0) & (dec_z == 3'h0) & dec_y[2];
 assign is_ld_rr_nnnn = (dec_x == 2'h0) & (dec_z == 3'h1) & ~dec_q & (dec_p != 2'h3);
 assign is_ld_sp_nnnn = (dec_x == 2'h0) & (dec_z == 3'h1) & ~dec_q & (dec_p == 2'h3);
 assign is_ldi_hl_a   = (dec_x == 2'h0) & (dec_z == 3'h2) & ~dec_q & (dec_p == 2'h2);
@@ -117,7 +117,7 @@ assign is_inc_r      = (dec_x == 2'h0) & (dec_z == 3'h4);
 assign is_dec_r      = (dec_x == 2'h0) & (dec_z == 3'h5);
 assign is_ld_r_n     = (dec_x == 2'h0) & (dec_z == 3'h6);
 assign is_ld_rr_a    = '0;
-assign is_rla        = (dec_x == 3'h0) & (dec_z == 3'h7) & (dec_y == 3'h2);
+assign is_rla        = (dec_x == 2'h0) & (dec_z == 3'h7) & (dec_y == 3'h2);
 
 assign is_ld_r_r     = (dec_x == 2'h1) & ((dec_z != 3'h6) | (dec_y != 3'h6));
 

rtl/cpu/regbank.sv

@@ -17,9 +17,7 @@ module regbank (
     input  reg8_t reg8_rselect_i,
     input  reg16_t reg16_rselect_i,
     output logic [ 7:0] reg8_rdata_o,
-    output logic [15:0] reg16_rdata_o,
+    output logic [15:0] reg16_rdata_o
-
-    output logic [15:0] hl_o
 );
 
     logic [15:0] reg_r   [0:2];
@@ -55,8 +53,6 @@ module regbank (
                                                reg_r[reg8_rselect_i[2:1]][15:8];
     assign reg16_rdata_o  = reg_r[reg16_rselect_i];
 
-    assign hl_o = reg_r[REG16_HL];
-
 `include "sva_common.svh"
 `SVA_DEF_CLK(clk)
 `SVA_DEF_NRESET(nreset)

rtl/ppu/ppu.sv

@@ -1,3 +1,5 @@
+`define VSYNC_HACK
+
 module ppu (
   input  logic clk,
   input  logic nreset,
@@ -77,14 +79,18 @@ assign ly_next = (ly_sel & cpu_we_i)                 ? 8'h00 : // Clear on write
                  (lx_end_of_line & ~ly_end_of_frame) ? (ly_r + 8'h01) :
                                                         ly_r;
 
-assign lx_next = lx_end_of_line ? 8'h0 : (lx_r + 8'h01);
+assign lx_next = lx_end_of_line ? 9'h0 : (lx_r + 9'h01);
 
 assign ly_end_of_frame = ly_r > 8'd153;
 assign lx_end_of_line  = lx_r > 9'd456;
 
 assign cpu_rdata_o =
   {8{lcdc_sel}} & lcdc_r |
+`ifdef VSYNC_HACK
+  {8{  ly_sel}} &   8'h90 |
+`else
   {8{  ly_sel}} &   ly_r |
+`endif
   {8{  sy_sel}} &   sy_r;
 
 `undef IOREG_DEF

sim/clkgen.sv

@@ -7,9 +7,9 @@ RESET_DELAY_NS = 45
 );
 
 initial begin
-  clk    <= 1'b1;
+  clk    = 1'b1;
-  nreset <= 1'b0;
+  nreset = 1'b0;
-  #RESET_DELAY_NS nreset <= 1'b1;
+  #RESET_DELAY_NS nreset = 1'b1;
 end
 
 always