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Initial work on build system

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Simple makefile to build testbench in vivado.
Testbench currently just has a clock and a reset.
Empty gb top module.
This commit is contained in:
Koray Yanik
2021-02-15 21:40:12 +00:00
parent 1a6259caa1
commit e56afb8c9e
6 changed files with 40 additions and 0 deletions
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build/tb_top.Makefile Normal file
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TB = tb_top
SOURCES = gb.sv tb_top.sv
PATH_SRC = ../rtl:../sim/tbench
include ../synthflow/vivado/Makefile.rules