Initial work on build system
Simple makefile to build testbench in vivado. Testbench currently just has a clock and a reset. Empty gb top module.
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build/.Xil
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build/xsim.dir
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[submodule "synthflow"]
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path = synthflow
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url = gitea:fumyuun/synthflow.git
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TB = tb_top
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SOURCES = gb.sv tb_top.sv
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PATH_SRC = ../rtl:../sim/tbench
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include ../synthflow/vivado/Makefile.rules
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module gb (
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input logic clk_i,
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input logic nreset_i
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);
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endmodule : gb
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module tb_top ();
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logic clk;
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logic nreset;
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gb gb_inst (
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.clk_i (clk),
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.nreset_i(nreset)
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);
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initial begin
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clk = 1'b0;
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nreset = 1'b1;
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#1 nreset = 1'b0;
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#24 nreset = 1'b1;
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end // initial
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always #5 clk = ~clk;
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endmodule : tb_top
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Subproject commit 767277e341012aa54acd72d26be9ea2fc921ca0c
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