Initial work on build system

Simple makefile to build testbench in vivado.
Testbench currently just has a clock and a reset.
Empty gb top module.

rtl/gb.sv

@@ -0,0 +1,8 @@
+module gb (
+    input  logic clk_i,
+    input  logic nreset_i
+);
+
+
+
+endmodule : gb