|
|
b1b2055db9
|
Fix another bug in 8bit register writing
|
2021-02-20 20:52:02 +00:00 |
|
|
|
67578ab87f
|
Fix bug in registers when loading 8bit values
|
2021-02-20 15:56:38 +00:00 |
|
|
|
67361093ec
|
Implement LD r, $nn
|
2021-02-20 15:56:22 +00:00 |
|
|
|
7327ecffb9
|
Implement JR CC, $nn
|
2021-02-20 15:55:31 +00:00 |
|
|
|
93912e2089
|
Implemented BIT $n, r
First of the CB prefixed opcodes.
|
2021-02-19 21:53:13 +00:00 |
|
|
|
8c65e4a669
|
Fix some typo's
|
2021-02-19 21:49:38 +00:00 |
|
|
|
8f0b8d3a48
|
Implemented LDD (HL), A
|
2021-02-18 23:22:26 +00:00 |
|
|
|
3e92cf5eec
|
Fix LD RR,$nnnn instruction not reading operand
|
2021-02-18 09:27:17 +00:00 |
|
|
|
2937ff492b
|
Initial register bank, support LD RR, $nnnn instructions
|
2021-02-17 22:40:24 +00:00 |
|
|
|
237a5f1489
|
Implemented SP, $nnnn and XOR A instructions
|
2021-02-16 23:05:46 +00:00 |
|
|
|
aa92344d10
|
Initial work on decoder
Decode the LD SP, $nnnn instruction as our first three-byte
instruction.
|
2021-02-16 21:13:50 +00:00 |
|
|
|
3191a19f7e
|
Initial work on reading instructions from bootROM
|
2021-02-15 22:55:09 +00:00 |
|
|
|
e56afb8c9e
|
Initial work on build system
Simple makefile to build testbench in vivado.
Testbench currently just has a clock and a reset.
Empty gb top module.
|
2021-02-15 21:40:12 +00:00 |
|
