06746f71fb
WIP PPU LX/LY registers
...
Removed second reg16 read port - no longer needed.
2023-10-03 20:44:28 +01:00
7cec002e1a
Starting work on a simple cartridge
...
In order to get through bootstrap process
2023-10-02 21:56:19 +01:00
fda176d3b5
Complete rewrite from scratch, bootstrap WIP
...
Rewrite to use several bus multiplexers, resulting into a less messy
microarchitecture (hopefully). Some more room for cleanup though...
Supports every instruction from the bootstrap rom, more or less.
LY hacked at 0x90 to progress through vsync instantly.
No cartridge is present yet, so we will always fail checksum test and lock up.
2023-10-01 23:00:56 +01:00
e713f8de87
Implement RLA and POP RR
2022-02-08 23:53:02 +00:00
da29d148bf
Update synthflow and adapt makefile
2022-02-08 16:14:13 +00:00
2937ff492b
Initial register bank, support LD RR, $nnnn instructions
2021-02-17 22:40:24 +00:00
237a5f1489
Implemented SP, $nnnn and XOR A instructions
2021-02-16 23:05:46 +00:00
aa92344d10
Initial work on decoder
...
Decode the LD SP, $nnnn instruction as our first three-byte
instruction.
2021-02-16 21:13:50 +00:00
3191a19f7e
Initial work on reading instructions from bootROM
2021-02-15 22:55:09 +00:00
e56afb8c9e
Initial work on build system
...
Simple makefile to build testbench in vivado.
Testbench currently just has a clock and a reset.
Empty gb top module.
2021-02-15 21:40:12 +00:00
