 Dennis Brentjes
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4a2d2b4881
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Restructured Amaranth code to be able to import sibling modules
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2022-01-22 19:28:29 +01:00 |
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Dennis Brentjes
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7780e14887
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Fix SP1 connector mirror mistake
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2022-01-22 19:21:35 +01:00 |
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Dennis Brentjes
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386602a63c
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Fixes clock cycle delay in propagation of ExiClockState
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2022-01-11 23:01:48 +01:00 |
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Dennis Brentjes
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43fb4beb6e
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Makes a seperate component that handles the ExiClk
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2022-01-09 22:42:14 +01:00 |
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Dennis Brentjes
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f7106abe87
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Made new top level design which uses the shiftregister and connects leds and buttons
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2022-01-09 17:07:56 +01:00 |
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Dennis Brentjes
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e0f186c304
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Restructured the amaranth HDL files.
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2022-01-09 15:12:27 +01:00 |
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Dennis Brentjes
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fd323b44e1
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Initial commit.
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2022-01-07 23:15:38 +01:00 |