Schematic fixes (PCB placement/routing of new parts pending, F8 lists them):
- FTDI rewired to stock iceprog convention: FLASH_CS ADBUS3->ADBUS4,
CDONE ACBUS1->ADBUS6, CRESET ACBUS0->ADBUS7 (old pins NC). With a
blank 93LC46B (default 0403:6010) stock iceprog now works unmodified;
EEPROM workflow decided: ship blank, FT_PROG optional (keep VID/PID).
- TPS2116 PR1 divider: R3 200k->150k (C25755) - switchover now at
2.30-2.70V worst case instead of 20mV under the 3.3V rail.
- ETH_RST: R36 10k pull-up to ETH_3V3 (RSTn floats during FPGA config).
- Debug provisions: D6 green heartbeat LED (C72043) on FPGA pin 47,
D7 red EXI-activity LED (C2286) on pin 48, 330R C25104 series; J4
6-pin LA header (GND + DBG0-4 = pins 9/10/11/12/6, unpopulated);
TP1-TP5 test points (3V3/1V2/ETH_3V3/GC_ON/GND, in_bom no); FID1-3
fiducials placed board-only on the PCB, track-clearance checked.
- Embedded Device:LED / Connector:TestPoint / Conn_01x06 lib symbols.
Closed by analysis (no change): TPS22810 CT cap unnecessary (DS Table 2:
~98us rise at 3.3V with CT=0 -> ~0.5A inrush); RSET_BG 12.4k accepted
(12.3k is E192; WIZnet ref synthesizes it as 12k+300R; 0.8% immaterial).
Verified: ERC 0; netlist 132 vs BOM 125 differing only by the 7
deliberate in_bom=no items (J3, J4, TP1-5); LED polarity and TP rails
confirmed in netlist; PCB DRC 0 errors with fiducials placed.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Re-verified every open item against the current board:
- All three critical findings (DO/DI swap, MDI termination incl.
dampers + center-tap bypass, FTDI EEPROM resistors) now done in both
schematic and PCB - marked resolved with review results
- Marked verified-done: 12V cap ratings, 1% tolerances, .history
ignore, fiducial check (absent - to add with debug pass)
- Confirmed still open: ETH_RST pull-up, PR1 divider margin (R3 still
200k), RSET 12.4k vs 12.3k, TPS22810 CT, iceprog pin mapping, board
PCF, debug LEDs/test points, mechanical fit, ordering options
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Completes the WIZnet reference schematic for the MDI section:
- R32-R35 3.3R 1% (YAGEO RC0402FR-073R3L, LCSC C137986) in series in
each MDI line per WIZnet note 6 (EMI damping). Chain per line is now
U11 pin -> 49.9R termination tap -> 3.3R -> D4/D5 flow-through -> J2.
Chip-side nets keep PHY_*; the D4/D5-side segments are renamed MDI_*
and added to the ETH_DP netclass patterns so the impedance DRC rules
police both halves.
- C20 100nF (C1525) + C21 1uF (C15849) on ETH_3V3 per WIZnet note 7 -
to be placed AT J2 pins 4/5 tapping the In2 ETH_3V3 island.
(Also carries KiCad's resave/reposition of ethernet.kicad_sch from the
rework session - netlist-identical, verified.)
Verified: ERC 0, netlist 121 components vs BOM 120 (J3-only delta),
PHY_TX_P = {U11.3, R26.1, R32.1}, MDI_TX_P = {R32.2, D4.1}, and
likewise for all four lines. PCB: 6 footprints to place (cut the lines
between termination and D4/D5 for R32-R35; C20/C21 at the jack).
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Record the verdict so it isn't relitigated: USBLC6 is ST-rated for
Ethernet, PHY-side placement is standard practice, floating VBUS is
deliberate (3.3V-biased lines would clip against a tied rail), and the
split PHY_*/ETH_* nets force zero-stub flow-through routing - the
better ESD topology. Earlier stub/DNP suggestion withdrawn.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
The 93LC46B's DO and DI were both tied directly to EEDATA, causing
drive contention during EEPROM read turnaround. Per the FT2232H
datasheet ("Connect directly to Data-In of the EEPROM and to Data-Out
of the EEPROM via a 2.2K resistor. Also, pull Data-Out of the EEPROM
to VCC via a 10K resistor"):
- U7.4 (DO) moved onto new net EE_DO
- R30 2.2k (UNI-ROYAL 0402WGF2201TCE, LCSC C25879, Basic) between
EE_DO and EE_DATA
- R31 10k (0402WGF1002TCE, C25744) pull-up from EE_DO to 3V3
- EEDATA -> DI (U7.3) stays direct
Schematic only; R30/R31 still need placing near U7 in the PCB rework.
Verified: ERC 0, EE_DATA = {U8.61, U7.3, R30.2}, EE_DO = {U7.4, R30.1,
R31.2}, R31.1 on global /Power/3V3 (no orphan local net), netlist
115 vs BOM 114 differing only by the deliberate J3 exclusion.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
The BOM was already fully populated (112/113 parts with MPN+LCSC) - this
audits it against the hardware-review requirements and closes the gaps:
- J3 (SP1 edge connector) set to in_bom=no: it is PCB gold fingers, not
a purchasable part. Netlist-vs-BOM count check now differs by exactly
this one deliberate exclusion.
- Crystals verified CL=12pF (Y1 C70565, Y2 C9006, both JLC Basic) -
matches the 18pF load caps and W5100S Table 9. TODO item closed.
- 12V-rail caps verified >=25V (C3/C4 25V, C6 50V, C65 Lelon 25V SMD
electrolytic); divider/REF/RSET resistors verified 1%.
- Noted: D2 LCSC C49383400 is the ElecSuper PUSB3AB6Z(ES) clone of the
Nexperia part (same DFN-7 package, 0.15pF) - pin-compatible.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Per the WIZnet W5100S reference schematic (note 4: "to avoid the 100M
overshoot, place the 49.9 resistors and 0.1uF capacitor near the MDI
pin"): R26/R27 (49.9R 1%) from TXOP/TXON to a common node bypassed by
C18 (100nF) to GND, and R28/R29 + C19 likewise for RXIP/RXIN. Attached
on the PHY-side nets (chip side of D4/D5). BOM fields populated
(UNI-ROYAL 0402WGF4999TCE / LCSC C25120, Samsung CL05B104KO5NNNC /
C1525). Optional 3.3R series dampers deliberately omitted.
Schematic only - the 6 footprints still need placing/routing next to
U11 pins 2/3/5/6 (Update PCB from Schematic). DRC parity reports
exactly those 6 missing footprints and nothing else.
Verified: ERC 0, netlist 107->113 components, termination nets match
the reference topology.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
SP1 DO/DI naming is console-perspective (verified against SD Gecko and
SD2SP2 wiring): pin 6 DO = GC data out = adapter MOSI input, pin 9 DI =
GC data in = adapter MISO output. The design doc's SP1 table had the
roles reversed and the schematic followed it, putting the FPGA's MISO
driver on the GC-driven DO line (bus contention).
Fix keeps all PCB routing identical:
- Swap net names EXI_MOSI(_RAW) <-> EXI_MISO(_RAW) across exi/Fpga/root
sheets and the PCB (also renames the D2 PUSB3AB6 channel assignments).
- Swap R21 (22R) <-> R25 (33R) identities between the two footprint
positions so 33R stays on the FPGA-driven MISO line, 22R on the MOSI
input.
- Correct the SP1 pin table + MISO-tristate note in
docs/gc_bba_fpga_design.md (root cause).
Resulting board pin map (for the future board PCF): EXI_MOSI = FPGA
pin 4 (IOB_8a, input), EXI_MISO = pin 3 (IOB_9b, output).
Verified: ERC 0, DRC 0 errors with schematic parity 0, netlist shows
J3.6(DO)->R21->pin 4 and J3.9(DI)->R25->pin 3.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
- Remove stale lowercase power.kicad_sch (pre-rework draft; live sheet is
Power.kicad_sch). Both paths were git-tracked, which on a case-insensitive
Windows checkout makes them one file on disk - deleting the stale one also
deleted the live one, and restoring the live sheet resurrected the stale
path at the next commit. Removing the path from the index breaks the loop.
- Remove re-bba-rb.kicad_pcb.old.* leftovers (recoverable from history).
- Restore hardware/re-bba-rb/datasheets/ (deleted accidentally by 3547302)
and add the two missing datasheets: TPS22810 (power) and PUSB3AB6 (exi).
- Add hardware/re-bba-rb/TODO.md capturing the 2026-07-17 review findings
(EXI DO/DI swap, missing W5100S MDI termination, FTDI EEPROM resistors,
iceprog pin mismatch, PR1 margin, BOM/ordering notes); referenced from
CLAUDE.md.
Verified after cleanup: ERC 0 violations, netlist identical (107 components).
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Dennis Brentjes
Roflin