Initial work on build system

Simple makefile to build testbench in vivado.
Testbench currently just has a clock and a reset.
Empty gb top module.

.gitignore

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+build/.Xil
+build/xsim.dir

.gitmodules

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+[submodule "synthflow"]
+	path = synthflow
+	url = gitea:fumyuun/synthflow.git

build/tb_top.Makefile

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+TB       = tb_top
+SOURCES  = gb.sv tb_top.sv
+PATH_SRC = ../rtl:../sim/tbench
+
+include ../synthflow/vivado/Makefile.rules

rtl/gb.sv

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+module gb (
+    input  logic clk_i,
+    input  logic nreset_i
+);
+
+
+
+endmodule : gb

sim/tbench/tb_top.sv

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+module tb_top ();
+
+    logic clk;
+    logic nreset;
+
+    gb gb_inst (
+        .clk_i   (clk),
+        .nreset_i(nreset)
+    );
+
+    initial begin
+        clk    = 1'b0;
+        nreset = 1'b1;
+
+        #1  nreset = 1'b0;
+        #24 nreset = 1'b1;
+    end // initial
+
+    always #5 clk = ~clk;
+
+endmodule : tb_top

synthflow

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+Subproject commit 767277e341012aa54acd72d26be9ea2fc921ca0c