Commit Graph

7 Commits

Author SHA1 Message Date
fda176d3b5 Complete rewrite from scratch, bootstrap WIP
Rewrite to use several bus multiplexers, resulting into a less messy
microarchitecture (hopefully). Some more room for cleanup though...

Supports every instruction from the bootstrap rom, more or less.
LY hacked at 0x90 to progress through vsync instantly.
No cartridge is present yet, so we will always fail checksum test and lock up.
2023-10-01 23:00:56 +01:00
4f892eb3f2 Implement RL r instruction
Some groundwork on rotation operations
2022-02-08 16:14:57 +00:00
49ce1631b3 Implement LD ($FF00+C), A 2021-02-20 22:10:47 +00:00
2937ff492b Initial register bank, support LD RR, $nnnn instructions 2021-02-17 22:40:24 +00:00
aa92344d10 Initial work on decoder
Decode the LD SP, $nnnn instruction as our first three-byte
instruction.
2021-02-16 21:13:50 +00:00
3191a19f7e Initial work on reading instructions from bootROM 2021-02-15 22:55:09 +00:00
e56afb8c9e Initial work on build system
Simple makefile to build testbench in vivado.
Testbench currently just has a clock and a reset.
Empty gb top module.
2021-02-15 21:40:12 +00:00