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7e558104de
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Implement ld a, rr
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2021-02-22 22:20:47 +00:00 |
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bd8df33066
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Rename decoding signals to be more consistent
r/n now always refers to 8bit registers, rr/nn to 16bit.
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2021-02-22 21:58:54 +00:00 |
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dc32757dfc
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Implement ld r, r
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2021-02-22 21:43:22 +00:00 |
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ded64a8954
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Implement inc r
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2021-02-20 22:57:15 +00:00 |
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49ce1631b3
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Implement LD ($FF00+C), A
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2021-02-20 22:10:47 +00:00 |
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b1b2055db9
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Fix another bug in 8bit register writing
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2021-02-20 20:52:02 +00:00 |
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67578ab87f
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Fix bug in registers when loading 8bit values
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2021-02-20 15:56:38 +00:00 |
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67361093ec
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Implement LD r, $nn
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2021-02-20 15:56:22 +00:00 |
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7327ecffb9
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Implement JR CC, $nn
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2021-02-20 15:55:31 +00:00 |
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93912e2089
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Implemented BIT $n, r
First of the CB prefixed opcodes.
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2021-02-19 21:53:13 +00:00 |
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8c65e4a669
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Fix some typo's
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2021-02-19 21:49:38 +00:00 |
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8f0b8d3a48
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Implemented LDD (HL), A
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2021-02-18 23:22:26 +00:00 |
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3e92cf5eec
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Fix LD RR,$nnnn instruction not reading operand
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2021-02-18 09:27:17 +00:00 |
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2937ff492b
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Initial register bank, support LD RR, $nnnn instructions
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2021-02-17 22:40:24 +00:00 |
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237a5f1489
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Implemented SP, $nnnn and XOR A instructions
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2021-02-16 23:05:46 +00:00 |
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aa92344d10
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Initial work on decoder
Decode the LD SP, $nnnn instruction as our first three-byte
instruction.
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2021-02-16 21:13:50 +00:00 |
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3191a19f7e
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Initial work on reading instructions from bootROM
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2021-02-15 22:55:09 +00:00 |
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e56afb8c9e
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Initial work on build system
Simple makefile to build testbench in vivado.
Testbench currently just has a clock and a reset.
Empty gb top module.
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2021-02-15 21:40:12 +00:00 |
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1a6259caa1
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Initial commit
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2021-02-15 14:54:08 +01:00 |
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